Product Summary

The CYD18S36V18-167BBXC belongs to FullFlex dual port SRAM family which consists of 2-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual port static RAMs that are high speed, low power 1.8 V or 1.5 V CMOS. Two ports are provided, enabling simultaneous access to the array. Simultaneous access to a location triggers deterministic access control. For FullFlex72 these ports operate independently with 72-bit bus widths and each port is independently configured for two pipelined stages. Each port is also configured to operate in pipelined or flow through mode.

Parametrics

CYD18S36V18-167BBXC absolute maximum ratings: (1)Storage temperature: –65 to + 150℃; (2)Ambient temperature with power applied: –55 to + 125 ℃; (3)Supply voltage to ground potential:–0.5 V to + 4.1 V; (4)DC voltage applied to outputs in high Z State: –0.5 V to VDDIO + 0.5 V; (5)DC input voltage: –0.5 V to VDDIO + 0.5 V; (6)Output current into outputs (LOW): 20 mA; (7)Static discharge voltage: > 2200 V; (8)(JEDEC JESD8-6, JESD8-B) Latch-up current: > 200 mA.

Features

CYD18S36V18-167BBXC features: (1)True dual port memory enables simultaneous access to the shared array from each port; (2)Synchronous pipelined operation with single data rate (SDR)operation on each port; (3)SDR interface at 200 MHz; (4)Up to 28.8 Gb/s bandwidth (200 MHz × 72-bit × 2 ports); (5)Selectable pipelined or flow-through mode; (6)1.5 V or 1.8 V core power supply; (7)Commercial and Industrial temperature; (8)IEEE 1149.1 JTAG boundary scan; (9)Available in 484-ball PBGA (× 72) and 256-ball FBGA (× 36 and × 18) packages; (10)Built in deterministic access control to manage address collisions; (11)Advanced features for improved high speed data transfer and flexibility.

Diagrams

CYD18S36V18-167BBXC logic block diagram

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CYD18S36V18-167BBXC
CYD18S36V18-167BBXC

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(USD)
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CYD18S18V18-167BBAXI
CYD18S18V18-167BBAXI

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